Computer systems typically use inexpensive and high-density dynamic random access memory (DRAM) chips for main memory. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards promulgated by the Joint Electron Devices Engineering Council (JEDEC). DDR DRAMs offer both high performance and low power operation by providing various low power modes.
Modern DDR memory controllers maintain queues to store pending memory access requests to allow them to pick the pending memory access requests out of order to increase efficiency. For example, the memory controllers can retrieve multiple memory access requests to the same row in a given rank of memory from the queue out of order and issue them consecutively to the memory system to avoid the overhead of precharging the current row and activating another row. However certain program threads repetitively access the same rank, bank, and page. Known memory controllers that group and select similar accesses to promote efficiency can “starve” other program threads and decrease overall system performance.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.